1. Field of the Invention
The present invention relates to a method for heat treatment of an SOI wafer, and particularly to a method for heat treatment capable of reducing crystal originated particle (hereinafter referred to as COP) density in the surface of an SOI layer while preventing etching of the SOI layer and a buried oxide layer.
2. Description of the Related Art
There has been proposed a technique such that an SOI (Silicon on Insulator) wafer is heat-treated at 500-1200.degree. C. in a reducing atmosphere of 200 Torr or less in order to improve the surface roughness of the SOI wafer (see Japanese Patent Application Laid-Open (kokai) No. 5-217821). This patent publication states that when an SOI wafer is heat-treated at 950.degree. C. in a hydrogen atmosphere of 80 Torr or less, the surface roughness of the SOI layer is improved from 20 nm to 1.5 nm.
In this case, the SOI layer of the SOI wafer is formed from an epitaxial layer.
Meanwhile, through performing experiments, the inventors of the present invention found that in an SOI wafer whose SOI layer is formed from a silicon wafer produced in accordance with the CZ (Czochralski method), when the SOI wafer undergoes hydrogen annealing at a high temperature of 1150.degree. for a long time of 180 minutes in accordance with the conventional method, silicon of the active layer (SOI layer) of the SOI wafer is etched by an amount of 0.5 .mu.m and etch pits are formed in a buried oxide layer. They also found that defects such as COPs (Crystals Originated Particles) are present in the SOI layer and that when such defects extend to a substrate oxide film, there occurs a disadvantageous phenomenon such that the COPs remain uneliminated or may even expand and that the buried oxide layer is etched by hydrogen that invades into the oxide layer through defects, resulting in formation of pits and adversely affecting the active layer in the vicinity thereof.
In order to counter the effects of such a phenomenon, the applicant of the present invention has proposed a technique in which heat treatment is performed in a state in which an SOI layer has a thickness greater than 0.5 .mu.m (see Japanese Patent Application Laid-Open (kokai) No. 10-84100. This method has a drawback of necessity for a step of reducing the thickness of the SOI layer after heat treatment in order to obtain an SOI layer having a thickness of 0.5 .mu.m or less.
Also, there was proposed a method in which a Si epitaxial layer is grown on a silicon wafer, which is then bonded to another wafer in order to use the epitaxial layer as an SOI layer. This method can reliably eliminate defects but greatly increases production costs.
Further, the above-described hydrogen annealing method is described as requiring at least one hour for high temperature heat treatment, with the result that the productivity is low. Further, since the heat treatment is performed in a batch scheme using a vertical type furnace, a large amount of hydrogen must be caused to flow through the furnace, thereby increasing danger involved in the use of hydrogen.
Meanwhile, presence of COPs has recently been reported to be a cause of decreasing the yield of a device fabricating process. COPs are one kind of crystal defect introduced during crystal growth and are known to have a regular octahedral structure.
When a mirror-polished silicon wafer is cleaned through use of a mixture solution comprising ammonium and hydrogen peroxide, pits are formed on the surface of the wafer. When particles on the thus-cleaned wafer are counted through use of a particle counter, in addition to real particles present on the wafer surface, pits are counted as particles. Such pits are called "COPs" in order to distinguish them from the real particles.
COPs present in the SOI layer of an SOI wafer cause degradation of electrical characteristics of the wafer.
For example, a reliability test which is the important electrical characteristics of a device, especially the time dependent dielectric breakdown (TDDB) of oxide film, relate to COPs, and therefore COPs must be decreased in order to improve TDDB.
Also, COPs are said to affect the time zero dielectric breakdown (TZDB) of oxide film.
Further, COPs are said to adversely affect a device fabrication process. That is, if COPs are present on the surface of an SOI wafer, steps are formed during a wiring process, which causes breakage of wires, resulting in decreased yield.